Convincing designers to change from a known technology in which they have developed a repertoire of skills to a new technology where the designers' skill-sets are not developed can be challenging. This is the nature of the problem faced by vendors of programmable gate arrays when attempting to convince a buyer that a programmable gate array will meet the buyer's requirements.
Many target customers for programmable gate arrays are designers who presently have ASIC design modules suitable for their applications. The ASIC design modules were likely developed using methodologies and design tools suitable for ASICs. Problems arise in convincing the designers that programmable gate arrays are suitable alternatives to ASICs because an ASIC design module, while perhaps optimally designed for the selected ASIC technology using ASIC design methodologies, may not translate to a programmable gate array design module that satisfies a designer's requirements. Quite often, the reason that an ASIC design module cannot be quickly translated to a design for a programmable gate array that performs acceptably is that the ASIC design module includes ASIC coding and design styles that are not compatible with FPGA design practices. The ASIC design module may also include design elements, for example, adders and multipliers, that are specifically tailored for the ASIC. Oftentimes, in order to convince a designer that a programmable gate array is suitable, field engineers are required to assist in analyzing, redesigning, and determining the performance and gate density of the programmable gate array for a given design. This process may take days or weeks. The outcome of the process may also be dependent on the particular expertise of the field engineer.
Therefore, a method and apparatus that addresses the aforementioned problems is therefore desirable.